Designing SOCs with Configured Cores

3.1. Introduction to Configurable Processor Architectures

The customary design method for achieving high performance at low clock rates—both at the board and chip level—is to design custom accelerator blocks. On SOCs, these are called RTL blocks and are most often manually developed using Verilog or VHDL. However, custom-designed RTL blocks are not usually firmware programmable because it takes a lot of extra design work to make them programmable. Consequently, most custom-designed logic blocks created for specific acceleration purposes are relatively inflexible. This inflexibility elevates design risk because an SOC that incorporates such blocks must be redesigned to accommodate any design changes brought on by bugs, specification changes, or ...