O'Reilly logo

Designing SOCs with Configured Cores by Steve Leibson

Stay ahead with the world's most comprehensive technology and business learning platform.

With Safari, you learn the way you learn best. Get unlimited access to videos, live online training, learning paths, books, tutorials, and more.

Start Free Trial

No credit card required

3.7. Base Xtensa Instructions

The base Xtensa ISA consists of more than 70 instructions in ten groups, listed in Table 3.1. Tables 3.23.9 give expanded explanations for the base instruction groups. These base instructions are sufficient to cover the needs of any program written in assembly language, C, or C++. For more performance, TIE instruction extensions can introduce nearly any instruction imaginable, as discussed in Chapter 4. Detailed explanations of the base Xtensa instructions appear in the Xtensa and Diamond Standard processor core data books.

Table 3.1. Base Xtensa ISA instruction summary
Instruction groupInstructions
LoadL8UI, L16SI, L16UI, L32I, L32R
StoreS8I, S16I, S32I
Memory OrderingMEMW, EXTW
Jump, CallCALL0, CALLX0, RETJ, JX
Conditional ...

With Safari, you learn the way you learn best. Get unlimited access to videos, live online training, learning paths, books, interactive tutorials, and more.

Start Free Trial

No credit card required