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Designing SOCs with Configured Cores by Steve Leibson

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4.8. TIE Ports

A processor’s I/O capabilities are often overshadowed by discussions of ISAs and pipeline architectures. However, I/O bandwidth has a substantial influence on a processor’s overall performance. Most processor core designs are limited to one main bus and a few local-memory buses. As discussed in previous chapters, buses immediately set processors apart from other sorts of hardware blocks. A bus conducts only one transaction per clock cycle so processors with only one bus to communicate with the rest of a system are similarly limited. The TIE language provides powerful ways to significantly boost the Xtensa processor’s I/O bandwidth through the addition of ports and queue interfaces.

Direct processor-to-processor port connections ...

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