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Designing SOCs with Configured Cores by Steve Leibson

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5.6. The PIF

The configurable PIF is the main-bus interface for Xtensa and Diamond Standard Series microprocessor cores. Xtensa PIFs can be configured to be 32, 64, or 128 bits wide. Pre-configured Diamond Standard Series processor cores have pre-configured PIF widths and the width depends on the Diamond core selected—higher performance Diamond cores have wider PIFs.

All Xtensa and Diamond core PIFs support single-data transactions (transactions that are less than or equal to the size of the data buses) as well as block transactions where several data-bus widths of data are input or output using multiple PIF-transaction cycles. The PIF employs a split-transaction protocol that accommodates multiple outstanding transaction requests. The PIF-transaction ...

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