O'Reilly logo

Designing SOCs with Configured Cores by Steve Leibson

Stay ahead with the world's most comprehensive technology and business learning platform.

With Safari, you learn the way you learn best. Get unlimited access to videos, live online training, learning paths, books, tutorials, and more.

Start Free Trial

No credit card required

5.8. SOC Connection Topologies

The large number and variety of interfaces on Xtensa and Diamond Standard Series processor cores creates a very wide architectural-design space. The PIF, local memory, and XLMI buses support all of the system topologies shown in Figures 5.15.5. In addition, the large number of buses, ports, and queues available on Xtensa and Diamond processor cores allows these processors to be employed in many novel system architectures that provide much higher I/O bandwidth than was previously possible with conventional microprocessor-based designs.

With Safari, you learn the way you learn best. Get unlimited access to videos, live online training, learning paths, books, interactive tutorials, and more.

Start Free Trial

No credit card required