The PIF is the Diamond processor’s main bus. The PIF has separate data buses for input and output transactions, and has an inbound-PIF request that allows external devices to access the Diamond processor core’s local memories. Figure 6.1 shows a single-data PIF read cycle and Figure 6.2 shows a single-data PIF write cycle. The PIF transaction protocol allows single-data transactions (less than or equal to the size of the data buses) as well as block transactions where several data-bus widths of data are input or output using multiple bus cycles. The PIF protocol employs split transactions and supports multiple outstanding requests. Speculative reads do not appear on the PIF.