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Designing SOCs with Configured Cores by Steve Leibson

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6.9. Zero-Overhead Loop Instructions

All of the Diamond cores except the 108Mini implement a set of zero-overhead loop instructions. Loops are a fundamental programming structure and are usually implemented with a processor’s decrement-test-and-branch instructions. Like all instructions, these instructions must be fetched and executed. These operations take time and create memory cycles and bus traffic, which can increase power dissipation. In addition, branch instructions inevitably create pipeline bubbles.

All of these considerations generate loop overhead. During these overhead cycles, the processor performs no useful work. The zero-overhead loop instruction uses three additional 32-bit registers to set up and keep track of loop conditions ...

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