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Designing SOCs with Configured Cores by Steve Leibson

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8.1. A General-Purpose Processor Core

Figure 8.1 is a block diagram of the Diamond 212GP controller core.

Figure 8.1. The Diamond 212GP controller core implements a full 32-bit RISC processor while consuming only 0.7 mm2 of silicon and 195 μW/MHz when implemented in a 130 nm, G-type process technology.

The Diamond 212GP processor architecture contains all of the basic elements of the Xtensa ISA. It has a 32-entry general-purpose register file, a 5-stage execution pipeline, 32-bit addressing, and a simple region-protection unit (RPU) that can be used to implement straightforward memory management. The Diamond 212GP core ...

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