Designing SOCs with Configured Cores

8.1. A General-Purpose Processor Core

Figure 8.1 is a block diagram of the Diamond 212GP controller core.

Figure 8.1. The Diamond 212GP controller core implements a full 32-bit RISC processor while consuming only 0.7 mm² of silicon and 195 μW/MHz when implemented in a 130 nm, G-type process technology.

The Diamond 212GP processor architecture contains all of the basic elements of the Xtensa ISA. It has a 32-entry general-purpose register file, a 5-stage execution pipeline, 32-bit addressing, and a simple region-protection unit (RPU) that can be used to implement straightforward memory management. The Diamond 212GP core ...

Get Designing SOCs with Configured Cores now with the O’Reilly learning platform.

O’Reilly members experience books, live events, courses curated by job role, and more from O’Reilly and nearly 200 top publishers.

Start your free trial

Designing SOCs with Configured Cores by Steve Leibson

8.1. A General-Purpose Processor Core

Figure 8.1. The Diamond 212GP controller core implements a full 32-bit RISC processor while consuming only 0.7 mm² of silicon and 195 μW/MHz when implemented in a 130 nm, G-type process technology.

Don’t leave empty-handed

It’s yours, free.

Check it out now on O’Reilly

8.1. A General-Purpose Processor Core

Figure 8.1. The Diamond 212GP controller core implements a full 32-bit RISC processor while consuming only 0.7 mm2 of silicon and 195 μW/MHz when implemented in a 130 nm, G-type process technology.

Don’t leave empty-handed

It’s yours, free.

Check it out now on O’Reilly

Figure 8.1. The Diamond 212GP controller core implements a full 32-bit RISC processor while consuming only 0.7 mm² of silicon and 195 μW/MHz when implemented in a 130 nm, G-type process technology.