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Designing SOCs with Configured Cores by Steve Leibson

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8.5. The 212GP RPU

The Diamond 212GP controller core uses the same RPU discussed in the previous chapter. However, the Diamond RPU’s cache-access modes are operational in the Diamond 212GP processor because it has instruction and data caches.

Figure 8.4 shows how the Diamond RPU divides the Diamond 212GP processor’s 4-Gbyte memory space into eight equally sized, 512-Mbyte regions. The Diamond 212GP controller core’s local data-memory address space and the address space assigned to the XLMI port fall into memory-protection region 1. Its local instruction-memory address space falls into memory-protection region 2. Thus the RPU can prevent accidental writes to instruction memory through the proper use of its protection mechanisms. The Diamond 212GP ...

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