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Designing SOCs with Configured Cores by Steve Leibson

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9.3. The Diamond 232L CPU Memory Map

The Diamond 232L CPU core’s entire address space is mapped to the PIF bus. The processor directs all instruction fetches, loads, stores, and cache spills and fills through the PIF. Table 9.1 lists the Diamond 232L CPU core’s assigned reset, non-maskable interrupt (NMI), and other interrupt vectors. The Diamond 232L’s reset and exception vectors are assigned to locations located in high memory, so some memory must be located at addresses 0xD0000000 to 0xD00003FF and 0xFE000000. In reality, the Diamond 232L CPU will be used for running large operating systems, so a large part of this upper address space will be populated with PIF-attached RAM.

Table 9.1. Diamond 232L processor reset, interrupt, and exception ...

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