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Designing SOCs with Configured Cores by Steve Leibson

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9.4. The Diamond 232L Cache Interfaces

Processor cache memories use fast, small RAM arrays to buffer the processor from the slower and larger memories generally located external to the processor core or the SOC. The Diamond 232L CPU core’s data and instruction caches store data and instructions that a program is immediately using, while the rest of the data and program reside in slower main memory—RAM, or ROM. In general, the Diamond 232L CPU core can access instruction and data caches simultaneously, which maximizes processor bandwidth and efficiency.

The Diamond 232L processor incorporates a pre-configured version of the Xtensa cache controller that operates separate, 16-Kbyte, 4-way, set-associative, instruction and data caches. The data ...

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