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Designing SOCs with Configured Cores by Steve Leibson

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10.2. Diamond 570T CPU Core Interfaces

As shown in Figure 10.3, the Diamond 570T CPU core has a 64-bit implementation of the Xtensa PIF (main processor interface) bus and separate interfaces for the 2-way set-associative instruction and data caches. The Diamond 570T CPU core also has 64-bit interfaces for local instruction and data memories, and a 64-bit XLMI port.

Figure 10.3. The Diamond 570T CPU core has a 64-bit implementation of the Xtensa PIF (main processor interface) bus and separate 64-bit interfaces for the 2-way, set-associative instruction and data caches; 64-bit interfaces for local instruction and data memories; and a 64-bit XLMI port.

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