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Designing SOCs with Configured Cores by Steve Leibson

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10.8. System Design with the Diamond 570T CPU Core

Figure 10.7 shows a simple one-dimensional systolic-processing system built with three Diamond 570T CPU cores (each with its own local memory), a large global memory, and two FIFO queues linking the three processor cores. The three Diamond 570T CPU cores communicate with each other through the global memory over the shared 64-bit PIF bus and they can pass information from CPU core #1 to CPU core #2 and then to CPU core #3 through the attached FIFOs. A bus arbiter and locking device control access to the PIF bus.

Figure 10.7. This systolic-processing system uses three Diamond 570T CPU cores linked with FIFOs to create a high-speed, flow-through processing system.

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