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Designing SOCs with Configured Cores by Steve Leibson

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12.2. A High-Performance DSP Core

The Diamond 545CK DSP core brings the performance benefits of a full-featured 32-bit RISC CPU to bear on the designated tasks:

  • Large 4-Gbyte address space

  • 32-bit computations

  • Large 32-entry register file

  • 128-bit interface ports for one local instruction RAM and two local data RAMs

  • 5-stage pipelined operation resulting in a 233-MHz maximum clock rate in 130 nm G-type (general-purpose) technology

  • Power dissipation is 255μ W/MHz and area is 5.14 mm2 in 130 nm LV (high-performance) technology.

The Diamond 545CK DSP core has a 128-bit version of the general-purpose PIF bus for global SOC communications. An optional AMBA bus bridge supplied with the Diamond 545CK DSP core adapts the PIF to peripheral devices designed for ...

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