Designing SOCs with Configured Cores

12.3. Diamond 545CK DSP Core Interfaces

As shown in Figure 12.3, the Diamond 545CK DSP core has a 128-bit implementation of the Xtensa PIF (main processor interface) bus and separate interfaces for the one local instruction RAM and two local data RAMs. Note that each of the two load/store units in the Diamond 545CK DSP core has its own interface port to each local data memory. External circuitry must connect both local ports to the associated local data memory and must arbitrate between the two load/store ports when simultaneous access occurs. There is only one instruction-fetch unit in the core, so there is only one port to local instruction memory.

Figure 12.3. The Diamond 545CK DSP core has a 128-bit implementation of the Xtensa PIF (main ...