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Designing SOCs with Configured Cores by Steve Leibson

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14.8. The Single-Bus Bottleneck

The sole data highway into and out of most processor cores is the main processor bus. Because processors often interact with other types of bus masters including other processors and DMA controllers, their main buses have sophisticated transaction protocols and arbitration mechanisms for sharing the bus among masters. These extra mechanisms result in bus transactions that occur over several clock cycles.

Read transactions on the Xtensa LX processor’s main bus (PIF) take a minimum of six cycles and a write transaction takes at least one cycle, depending on the speed of the target device connected to the PIF. From these transaction timings, we can calculate the minimum number of cycles needed to perform a simple ...

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