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Designing SOCs with Configured Cores by Steve Leibson

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15.1.2. SOC Disaster Scenario 2: Excessive System Power Dissipation

Since the introduction and widespread adoption of the 130-nm process node, classical device scaling no longer delivers the same large drops in power and energy to compensate for the increased number of available transistors. At the same time, increasingly ambitious SOC performance goals have emphasized the use of faster and faster clock rates at the expense of power dissipation. The net result is ever-higher SOC energy consumption in an era that increasingly values end-product performance characteristics such as battery-life, talk time, and compactness. All of these valued end-product characteristics are at odds with increased SOC energy consumption.

The trends are clear. Disaster ...

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