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Designing SOCs with Configured Cores by Steve Leibson

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15.1.5. SOC Disaster Scenario 5: Deteriorating Chip Reliability

All SOC designs can fail due to manufacturing defects. Nanometer ICs are more susceptible to manufacturing errors due to their finer geometries. Flaws are best caught on the manufacturing floor during testing because the repair cost of a chip failure is much higher after the chips are in the field. If properly designed, the same redundancy added to ICs to counter-manufacturing defects can serve double duty as a way to patch failures in fielded systems.

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