The three largest causes of on-chip signal interference are:
Close wire proximity caused by nanometer design rules.
High coupling factors caused by long adjacent wire runs.
Increased coupling caused by high clock frequencies and sharp signal edges.
A processor-centric system-level design style attacks causes 2 and 3. Assigning tasks to processors creates task islands and reduces the need for large global buses that convey large numbers of signals across long stretches of the SOC. Task-specific processor tailoring reduces the need for high-operating clock frequencies.