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Designing SOCs with Configured Cores by Steve Leibson

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15.2.4. Avoiding Disaster Scenario 4: Excessive Signal Interference

The three largest causes of on-chip signal interference are:

  1. Close wire proximity caused by nanometer design rules.

  2. High coupling factors caused by long adjacent wire runs.

  3. Increased coupling caused by high clock frequencies and sharp signal edges.

A processor-centric system-level design style attacks causes 2 and 3. Assigning tasks to processors creates task islands and reduces the need for large global buses that convey large numbers of signals across long stretches of the SOC. Task-specific processor tailoring reduces the need for high-operating clock frequencies.

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