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Designing SOCs with Configured Cores by Steve Leibson

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Preface

In the 21st century, system-on-chip (SOC) design styles are changing. Not because they can but because they must. Moore’s law and the side benefits of classical semiconductor scaling (faster transistors running at lower power at each new processing node) parted company when the semiconductor industry hit the 130 nm processing node just after the turn of the century. As a result, on-chip clock rates stopped rising as quickly as they had and power levels stopped falling as quickly as they had. These two side effects of lithographic scaling, usually (and incorrectly) attributed to Moore’s law, were actually developed by IBM’s Robert Dennard and his team in the early 1970s. On-chip clock rate and power dissipation have tracked Moore’s law ...

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