Digital Design of Signal Processing Systems: A Practical Approach

Index

2’s Complement Numbers

Complement Computation

Scaling

2’s Complement Representation

2’s Complement Signed Multiplier

5:3 bit counter

5/3 lifting wavelet

4-entry FIFO queue

6:3 counter

(Advanced Microcontroller Bus Architecture) AMBA

A Hybrid FIR filter Structure

A multi channel DMA design

Acoustic Echo Canceller

Acoustic Noise Cancellation

Adaptive Algorithms

ADC bandwidth (BW)

adder graphs

Adders

Example

AES Algorithm

AES Architectures

Byte Systolic Fully Parallel

Time-Shared 8-bit Folding Architecture

Algorithm Transformations for CSA

Algorithmic State Machine (ASM)

Always Procedural Block

Amba High-speed Bus (AHB)

Analog Front End (AFE)

analog mixers

Application Specific Instruction-set Processor (ASIP)

Application Specific Processor (ASP)

Arithmetic Operators

Arithmetic Shift

ASICs

ASM

Example

ASM representation Blocks

assign

Balanced Equations

Example

Bandpass Sampling

Example

Barrel Shifter

dedicated multiplier

hierarchical design

pipelined design

Behavioral Level

Binary Carry Look-ahead Adder (BCLA)

Serial Implementation

Han-Carlson Parallel Prefix Adder

Kogge-Stone Parallel Prefix Adder

Ladner-Fischer Parallel Prefix Adder

RTL Verilog code

Bit-serial architecture

Example

Bitwise Arithmetic Operators

Black Box Testing

Block Diagram

Block Floating-Point Format

Block LMS

Block Turbo Code (BTC)

Blocking Procedural Assignment

Brent-Kung

Bubble Diagrams

Bus-based Design

Canonic Sign Digit (CSD)

carrier and sampling clock frequency offsets

Carry Chain Logic in FPGAs

Carry ...