Digital Electronics and Design with VHDL

Digital Electronics and Design with VHDL

by Volnei A. Pedroni
Released January 2008
Publisher(s): Morgan Kaufmann
ISBN: 9780080557557

Read it now on the O’Reilly learning platform with a 10-day free trial.

O’Reilly members get unlimited access to books, live events, courses curated by job role, and more from O’Reilly and nearly 200 top publishers.

Start your free trial

Book description

Digital Electronics and Design with VHDL offers a friendly presentation of the fundamental principles and practices of modern digital design. Unlike any other book in this field, transistor-level implementations are also included, which allow the readers to gain a solid understanding of a circuit's real potential and limitations, and to develop a realistic perspective on the practical design of actual integrated circuits.

Coverage includes the largest selection available of digital circuits in all categories (combinational, sequential, logical, or arithmetic); and detailed digital design techniques, with a thorough discussion on state-machine modeling for the analysis and design of complex sequential systems. Key technologies used in modern circuits are also described, including Bipolar, MOS, ROM/RAM, and CPLD/FPGA chips, as well as codes and techniques used in data storage and transmission. Designs are illustrated by means of complete, realistic applications using VHDL, where the complete code, comments, and simulation results are included.

This text is ideal for courses in Digital Design, Digital Logic, Digital Electronics, VLSI, and VHDL; and industry practitioners in digital electronics.

  • Comprehensive coverage of fundamental digital concepts and principles, as well as complete, realistic, industry-standard designs
  • Many circuits shown with internal details at the transistor-level, as in real integrated circuits
  • Actual technologies used in state-of-the-art digital circuits presented in conjunction with fundamental concepts and principles
  • Six chapters dedicated to VHDL-based techniques, with all VHDL-based designs synthesized onto CPLD/FPGA chips

Table of contents

  1. Cover image
  2. Title page
  3. Table of Contents
  4. Copyright
  5. Dedication
  6. Preface
  7. Chapter 1: Introduction
    1. 1.1 Historical Notes
    2. 1.2 Analog versus Digital
    3. 1.3 Bits, Bytes, and Words
    4. 1.4 Digital Circuits
    5. 1.5 Combinational Circuits versus Sequential Circuits
    6. 1.6 Integrated Circuits
    7. 1.7 Printed Circuit Boards
    8. 1.8 Logic Values versus Physical Values
    9. 1.9 Nonprogrammable, Programmable, and Hardware Programmable
    10. 1.10 Binary Waveforms
    11. 1.11 DC, AC, and Transient Responses
    12. 1.12 Programmable Logic Devices
    13. 1.13 Circuit Synthesis and Simulation with VHDL
    14. 1.14 Circuit Simulation with SPICE
    15. 1.15 Gate-Level versus Transistor-Level Analysis
  8. Chapter 2: Binary Representations
    1. 2.1 Binary Code
    2. 2.2 Octal and Hexadecimal Codes
    3. 2.3 Gray Code
    4. 2.4 BCD Code
    5. 2.5 Codes for Negative Numbers
    6. 2.6 Floating-Point Representation
    7. 2.7 ASCII Code
    8. 2.8 Unicode
    9. 2.9 Exercises
  9. Chapter 3: Binary Arithmetic
    1. 3.1 Unsigned Addition
    2. 3.2 Signed Addition and Subtraction
    3. 3.3 Shift Operations
    4. 3.4 Unsigned Multiplication
    5. 3.5 Signed Multiplication
    6. 3.6 Unsigned Division
    7. 3.7 Signed Division
    8. 3.8 Floating-Point Addition and Subtraction
    9. 3.9 Floating-Point Multiplication
    10. 3.10 Floating-Point Division
    11. 3.11 Exercises
  10. Chapter 4: Introduction to Digital Circuits
    1. 4.1 Introduction to MOS Transistors
    2. 4.2 Inverter and CMOS Logic
    3. 4.3 AND and NAND Gates
    4. 4.4 OR and NOR Gates
    5. 4.5 XOR and XNOR Gates
    6. 4.6 Modulo-2 Adder
    7. 4.7 Buffer
    8. 4.8 Tri-State Buffer
    9. 4.9 Open-Drain Buffer
    10. 4.10 D-Type Flip-Flop
    11. 4.11 Shift Register
    12. 4.12 Counters
    13. 4.13 Pseudo-Random Sequence Generator
    14. 4.14 Exercises
  11. Chapter 5: Boolean Algebra
    1. 5.1 Boolean Algebra
    2. 5.2 Truth Tables
    3. 5.3 Minterms and SOP Equations
    4. 5.4 Maxterms and POS Equations
    5. 5.5 Standard Circuits for SOP and POS Equations
    6. 5.6 Karnaugh Maps
    7. 5.7 Large Karnaugh Maps
    8. 5.8 Other Function-Simplification Techniques
    9. 5.9 Propagation Delay and Glitches
    10. 5.10 Exercises
  12. Chapter 6: Line Codes
    1. 6.1 The Use of Line Codes
    2. 6.2 Parameters and Types of Line Codes
    3. 6.3 Unipolar Codes
    4. 6.4 Polar Codes
    5. 6.5 Bipolar Codes
    6. 6.6 Biphase/Manchester Codes
    7. 6.7 MLT Codes
    8. 6.8 mB/nB Codes
    9. 6.9 PAM Codes
    10. 6.10 Exercises
  13. Chapter 7: Error-Detecting/Correcting Codes
    1. 7.1 Codes for Error Detection and Error Correction
    2. 7.2 Single Parity Check (SPC) Codes
    3. 7.3 Cyclic Redundancy Check (CRC) Codes
    4. 7.4 Hamming Codes
    5. 7.5 Reed-Solomon (RS) Codes
    6. 7.6 Interleaving
    7. 7.7 Convolutional Codes
    8. 7.8 Viterbi Decoder
    9. 7.9 Turbo Codes
    10. 7.10 Low Density Parity Check (LDPC) Codes
    11. 7.11 Exercises
  14. Chapter 8: Bipolar Transistor
    1. 8.1 Semiconductors
    2. 8.2 The Bipolar Junction Transistor
    3. 8.3 I-V Characteristics
    4. 8.4 DC Response
    5. 8.5 Transient Response
    6. 8.6 AC Response
    7. 8.7 Modern BJTs
    8. 8.8 Exercises
  15. Chapter 9: MOS Transistor
    1. 9.1 Semiconductors
    2. 9.2 The Field-Effect Transistor (MOSFET)
    3. 9.3 I-V Characteristics
    4. 9.4 DC Response
    5. 9.5. CMOS Inverter
    6. 9.6 Transient Response
    7. 9.7 AC Response
    8. 9.8 Modern MOSFETs
    9. 9.9 Exercises
  16. Chapter 10: Logic Families and I/Os
    1. 10.1 BJT-Based Logic Families
    2. 10.2 Diode-Transistor Logic
    3. 10.3 Transistor-Transistor Logic (TTL)
    4. 10.4 Emitter-Coupled Logic
    5. 10.5 MOS-Based Logic Families
    6. 10.6 CMOS Logic
    7. 10.7 Other Static MOS Architectures
    8. 10.8 Dynamic MOS Architectures
    9. 10.9 Modern I/O Standards
    10. 10.10 Exercises
  17. Chapter 11: Combinational Logic Circuits
    1. 11.1 Combinational versus Sequential Logic
    2. 11.2 Logical versus Arithmetic Circuits
    3. 11.3 Fundamental Logic Gates
    4. 11.4 Compound Gates
    5. 11.5 Encoders and Decoders
    6. 11.6 Multiplexer
    7. 11.7 Parity Detector
    8. 11.8 Priority Encoder
    9. 11.9 Binary Sorter
    10. 11.10 Shifters
    11. 11.11 Nonoverlapping Clock Generators
    12. 11.12 Short-Pulse Generators
    13. 11.13 Schmitt Triggers
    14. 11.14 Memories
    15. 11.15 Exercises
    16. 11.16 Exercises with VHDL
    17. 11.17 Exercises with SPICE
  18. Chapter 12: Combinational Arithmetic Circuits
    1. 12.1 Arithmetic versus Logic Circuits
    2. 12.2 Basic Adders
    3. 12.3 Fast Adders
    4. 12.4 Bit-Serial Adder
    5. 12.5 Signed Adders/Subtracters
    6. 12.6 Incrementer, Decrementer, and Two’s Complementer
    7. 12.7 Comparators
    8. 12.8 Arithmetic-Logic Unit
    9. 12.9 Multipliers
    10. 12.10 Dividers
    11. 12.11 Exercises
    12. 12.12 Exercises with VHDL
    13. 12.13 Exercises with SPICE
  19. Chapter 13: Registers
    1. 13.1 Sequential versus Combinational Logic
    2. 13.2 SR Latch
    3. 13.3 D Latch
    4. 13.4 D Flip-Flop
    5. 13.5 Master-Slave D Flip-Flops
    6. 13.6 Pulse-Based D Flip-Flops
    7. 13.7 Dual-Edge D Flip-Flops
    8. 13.8 Statistically Low-Power D Flip-Flops
    9. 13.9 D Flip-Flop Control Ports
    10. 13.10 T Flip-Flop
    11. 13.11 Exercises
    12. 13.12 Exercises with SPICE
  20. Chapter 14: Sequential Circuits
    1. 14.1 Shift Registers
    2. 14.2 Synchronous Counters
    3. 14.3 Asynchronous Counters
    4. 14.4 Signal Generators
    5. 14.5 Frequency Dividers
    6. 14.6 PLL and Prescalers
    7. 14.7 Pseudo-Random Sequence Generators
    8. 14.8 Scramblers and Descramblers
    9. 14.9 Exercises
    10. 14.10 Exercises with VHDL
    11. 14.11 Exercises with SPICE
  21. Chapter 15: Finite State Machines
    1. 15.1 Finite State Machine Model
    2. 15.2 Design of Finite State Machines
    3. 15.3 System Resolution and Glitches
    4. 15.4 Design of Large Finite State Machines
    5. 15.5 Design of Finite State Machines with Complex Combinational Logic
    6. 15.6 Multi-Machine Designs
    7. 15.7 Generic Signal Generator Design Technique
    8. 15.8 Design of Symmetric-Phase Frequency Dividers
    9. 15.9 Finite State Machine Encoding Styles
    10. 15.10 Exercises
    11. 15.11 Exercises with VHDL
  22. Chapter 16: Volatile Memories
    1. 16.1 Memory Types
    2. 16.2 Static Random Access Memory (SRAM)
    3. 16.3 Dual and Quad Data Rate (DDR, QDR) SRAMs
    4. 16.4 Dynamic Random Access Memory (DRAM)
    5. 16.5 Synchronous DRAM (SDRAM)
    6. 16.6 Dual Data Rate (DDR, DDR2, DDR3) SDRAMs
    7. 16.7 Content-Addressable Memory (CAM) for Cache Memories
    8. 16.8 Exercises
  23. Chapter 17: Nonvolatile Memories
    1. 17.1 Memory Types
    2. 17.2 Mask-Programmed ROM (MP-ROM)
    3. 17.3 One-Time-Programmable ROM (OTP-ROM)
    4. 17.4 Electrically Programmable ROM (EPROM)
    5. 17.5 Electrically Erasable Programmable ROM (EEPROM)
    6. 17.6 Flash Memory
    7. 17.7 Next-Generation Nonvolatile Memories
    8. 17.8 Exercises
  24. Chapter 18: Programmable Logic Devices
    1. 18.1 The Concept of Programmable Logic Devices
    2. 18.2 SPLDs
    3. 18.3 CPLDs
    4. 18.4 FPGAs
    5. 18.5 Exercises
  25. Chapter 19: VHDL Summary
    1. 19.1 About VHDL
    2. 19.2 Code Structure
    3. 19.3 Fundamental VHDL Packages
    4. 19.4 Predefined Data Types
    5. 19.5 User Defined Data Types
    6. 19.6 Operators
    7. 19.7 Attributes
    8. 19.8 Concurrent versus Sequential Code
    9. 19.9 Concurrent Code (WHEN, GENERATE)
    10. 19.10 Sequential Code (IF, CASE, LOOP, WAIT)
    11. 19.11 Objects (CONSTANT, SIGNAL, VARIABLE)
    12. 19.12 Packages
    13. 19.13 Components
    14. 19.4 Functions
    15. 19.15 Procedures
    16. 19.16 VHDL Template for FSMs
    17. 19.17 Exercises
  26. Chapter 20: VHDL Design of Combinational Logic Circuits
    1. 20.1 Generic Address Decoder
    2. 20.2 BCD-to-SSD Conversion Function
    3. 20.3 Generic Multiplexer
    4. 20.4 Generic Priority Encoder
    5. 20.5 Design of ROM Memory
    6. 20.6 Design of Synchronous RAM Memories
    7. 20.7 Exercises
  27. Chapter 21: VHDL Design of Combinational Arithmetic Circuits
    1. 21.1 Carry-Ripple Adder
    2. 21.2 Carry-Lookahead Adder
    3. 21.3 Signed and Unsigned Adders/Subtracters
    4. 21.4 Signed and Unsigned Multipliers/Dividers
    5. 21.5 ALU
    6. 21.6 Exercises
  28. Chapter 22: VHDL Design of Sequential Circuits
    1. 22.1 Shift Register with Load
    2. 22.2 Switch Debouncer
    3. 22.3 Timer
    4. 22.4 Fibonacci Series Generator
    5. 22.5 Frequency Meters
    6. 22.6 Neural Networks
    7. 22.7 Exercises
  29. Chapter 23: VHDL Design of State Machines
    1. 23.1 String Detector
    2. 23.2 “Universal” Signal Generator
    3. 23.3 Car Alarm
    4. 23.4 LCD Driver
    5. 23.5 Exercises
  30. Chapter 24: Simulation with VHDL Testbenches
    1. 24.1 Synthesis versus Simulation
    2. 24.2 Testbench Types
    3. 24.3 Stimulus Generation
    4. 24.4 Testing the Stimuli
    5. 24.5 Testbench Template
    6. 24.6 Writing Type I Testbenches
    7. 24.7 Writing Type II Testbenches
    8. 24.8 Writing Type III Testbenches
    9. 24.9 Writing Type IV Testbenches
    10. 24.10 Exercises
  31. Chapter 25: Simulation with SPICE
    1. 25.1 About SPICE
    2. 25.2 Types of Analysis
    3. 25.3 Basic Structure of SPICE Code
    4. 25.4 Declarations of Electronic Devices
    5. 25.5 Declarations of Independent DC Sources
    6. 25.6 Declarations of Independent AC Sources
    7. 25.7 Declarations of Dependent Sources
    8. 25.8 SPICE Inputs and Outputs
    9. 25.9 DC Response Examples
    10. 25.10 Transient Response Examples
    11. 25.11 AC Response Example
    12. 25.12 Monte Carlo Analysis
    13. 25.13 Subcircuits
    14. 25.14 Exercises Involving Combinational Logic Circuits
    15. 25.15 Exercises Involving Combinational Arithmetic Circuits
    16. 25.16 Exercises Involving Registers
    17. 25.17 Exercises Involving Sequential Circuits
  32. A: ModelSim Tutorial
  33. B: PSpice Tutorial
  34. References
  35. Index

Product information

  • Title: Digital Electronics and Design with VHDL
  • Author(s): Volnei A. Pedroni
  • Release date: January 2008
  • Publisher(s): Morgan Kaufmann
  • ISBN: 9780080557557