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Digital Integrated Circuit Design Using Verilog and Systemverilog

Book Description

For those with a basic understanding of digital design, this book teaches the essential skills to design digital integrated circuits using Verilog and the relevant extensions of SystemVerilog. In addition to covering the syntax of Verilog and SystemVerilog, the author provides an appreciation of design challenges and solutions for producing working circuits. The book covers not only the syntax and limitations of HDL coding, but deals extensively with design problems such as partitioning and synchronization, helping you to produce designs that are not only logically correct, but will actually work when turned into physical circuits. Throughout the book, many small examples are used to validate concepts and demonstrate how to apply design skills.

This book takes readers who have already learned the fundamentals of digital design to the point where they can produce working circuits using modern design methodologies. It clearly explains what is useful for circuit design and what parts of the languages are only software, providing a non-theoretical, practical guide to robust, reliable and optimized hardware design and development.

  • Produce working hardware: Covers not only syntax, but also provides design know-how, addressing problems such as synchronization and partitioning to produce working solutions
  • Usable examples: Numerous small examples throughout the book demonstrate concepts in an easy-to-grasp manner
  • Essential knowledge: Covers the vital design topics of synchronization, essential for producing working silicon; asynchronous interfacing techniques; and design techniques for circuit optimization, including partitioning

Table of Contents

  1. Cover
  2. Title page
  3. Table of Contents
  4. Copyright Page
  5. About the author
  6. Preface
  7. Acknowledgments
  8. Chapter 1: Introduction
    1. Abstract
    2. Who should read this book
    3. Hardware description languages and methodology
    4. What this book covers
    5. Historical perspective
    6. Verilog and Systemverilog
    7. Book organization
  9. Chapter 2: Bottom-up design
    1. Abstract
    2. Primitive instantiation
    3. Designing with primitives
    4. Identifiers and escaped identifiers
    5. Bus declarations
    6. Design hierarchy and test fixtures
    7. Port association
    8. Timescales
    9. Summary
  10. Chapter 3: Behavioral coding part I: blocks, variables, and operators
    1. Abstract
    2. Top-down design
    3. Synthesizable and nonsynthesizable code
    4. Register Transfer Level (RTL)
    5. Continuous assignments
    6. Implicit continuous assignments
    7. Functional blocks: always and initial
    8. Named blocks
    9. Sensitivity lists
    10. Splitting assignments
    11. Variables
    12. Operators
    13. Summary
  11. Chapter 4: Behavioral coding part II: defines, parameters, enumerated types, and packages
    1. Abstract
    2. Global definitions
    3. Parameters
    4. Overriding default values
    5. Local parameters
    6. Specify parameters
    7. Enumerated types
    8. Constants
    9. Packages
    10. Filling a scalable variable with all ones
    11. Summary
  12. Chapter 5: Behavioral coding part III: loops and branches
    1. Abstract
    2. Loops
    3. Case statements
    4. Latch generation
    5. Unique and priority
    6. Summary
  13. Chapter 6: Subroutines and interfaces
    1. Abstract
    2. Subroutines
    3. Tasks
    4. Functions
    5. Parameters in subroutines
    6. Managing subroutines
    7. Interfaces
    8. Interface modports
    9. Summary
  14. Chapter 7: Synchronization
    1. Abstract
    2. Latch instability
    3. Flipflops, latches, and violations
    4. Asynchronous assert, synchronous deassert
    5. Slow-speed single-bit clocked asynchronous interfaces
    6. High-speed single-bit clocked asynchronous interfaces
    7. Multiple high-speed single-bit clocked asynchronous interfaces
    8. Asynchronous parallel buses
    9. High-speed asynchronous serial links
    10. Summary
  15. Chapter 8: Simulation, timing, and race conditions
    1. Abstract
    2. Simulation queues
    3. Race conditions
    4. Derived clocks and delta time
    5. Assertions
    6. Summary
  16. Chapter 9: Architectural choices
    1. Abstract
    2. FPGA versus ASIC
    3. Design reuse
    4. Partitioning
    5. Area and speed optimization
    6. Power optimization
    7. Summary
  17. Chapter 10: Design for testability
    1. Abstract
    2. Yield, testing, and defect level
    3. Fault modeling
    4. Activation and sensitization
    5. Logic scan
    6. Boundary scan
    7. Built in self-test
    8. Parametric testing
    9. Summary
  18. Chapter 11: Library modeling
    1. Abstract
    2. Component libraries
    3. Cell models
    4. User-defined primitives
    5. Combinational cells
    6. Sequential cells
    7. Model performance
    8. Summary
  19. Chapter 12: Design examples
    1. Abstract
    2. State machine
    3. FIR filters
    4. FIFO
    5. DMX receiver
  20. Appendix A: SystemVerilog keywords
  21. Appendix B: Standard combinational and sequential functions
  22. Appendix C: Number systems
  23. Index