Chapter 2

Bottom-up design

Abstract

This chapter introduces the most fundamental building blocks of a Verilog design. It shows how components can be used to build up a design hierarchy and includes several constructs needed to create and verify a design.

Keywords

primitive

instance

instantiation

identifier

module

port

hierarchical design

timescale

This chapter introduces the most fundamental building blocks of a Verilog design. It shows how components can be used to build up a design hierarchy and includes several constructs ...

Get Digital Integrated Circuit Design Using Verilog and Systemverilog now with O’Reilly online learning.

O’Reilly members experience live online training, plus books, videos, and digital content from 200+ publishers.