Skip to Main Content
Digital Integrated Circuit Design Using Verilog and Systemverilog
book

Digital Integrated Circuit Design Using Verilog and Systemverilog

by Ronald W. Mehler
September 2014
Intermediate to advanced content levelIntermediate to advanced
448 pages
9h 45m
English
Newnes
Content preview from Digital Integrated Circuit Design Using Verilog and Systemverilog
Chapter 8

Simulation, timing, and race conditions

Abstract

ASIC design methodology using a hardware design language is dependent on digital simulation. This simulation is an imperfect representation of how a real circuit will perform, but it is the most practical technique for initial design verification. Over the years numerous simulation algorithms have been developed. The thrust has always been to increase speed. The first digital simulators were time driven, where each node was evaluated at each instant of time. Since at any given time, only a small percentage of nodes will have changed from the previous instant, most of the computing effort was wasted. More modern algorithms are vastly more computationally efficient and modern simulators ...
Become an O’Reilly member and get unlimited access to this title plus top books and audiobooks from O’Reilly and nearly 200 top publishers, thousands of courses curated by job role, 150+ live events each month,
and much more.
Start your free trial

You might also like

Digital VLSI Design and Simulation with Verilog

Digital VLSI Design and Simulation with Verilog

Suman Lata Tripathi, Sobhit Saxena, Sanjeet K. Sinha, Govind S. Patel

Publisher Resources

ISBN: 9780124080591