Digital Integrated Circuit Design Using Verilog and Systemverilog

Chapter 12

Design examples

Abstract

This chapter shows implementations of designs referenced in earlier chapters. Included are complete, synthesizable designs for a state machine, several different filter designs, a FIFO and an asynchronous bit-serial interface. It also includes some test programs for the included designs.

Keywords

state machine

finite impulse response

FIR filter

FIFO

DMX512

Outline

 State machine 361

 FIR filters 364

 FIFO 376

 DMX receiver 382

This chapter shows implementations of designs referenced in earlier chapters. Included are complete, synthesizable designs for a state machine, several different filter designs, a FIFO and an asynchronous bit-serial interface. It also includes some test programs for the included ...