Digital Logic Testing and Simulation, 2nd Edition

CHAPTER 3

Fault Simulation

3.1 INTRODUCTION

Thus far simulation has been considered within the context of design verification. The purpose was to determine whether or not the design was correct. Were all the key control signals of the design checked out? What about the data paths, were all the “corners” or endpoints checked out? Are we confident that all likely combinations of events have been simulated and that the circuit model responded correctly? Is the design ready to be taped out?

We now turn our attention to simulation as it relates to manufacturing test. Here the objective is to create a test program that uncovers defects and performance problems that occur during the manufacturing process. In addition to being thorough, a test program must also be efficient. If design verification involves a large number of redundant simulations, there is unnecessary delay in moving the design to tape-out. If the manufacturing test program involves creation of redundant test stimuli, there is delay in migrating the test program to the tester. However, stimuli that do not improve test thoroughness also add recurring costs at the tester because there is the cost of providing storage for all those test stimuli as well as the cost of applying the excess stimuli to every chip that is manufactured.

There are many similarities between design verification and manufacturing test program development, ...