Clocking in high-performance digital systems is most seriously affected by clock skew and clock jitter. In the past, clock skew was the dominant factor. Recently, however, clock jitter has started gaining dominance over clock skew. Here we will treat both of them as clock uncertainties. With the recent trend in frequency scaling, the number of logic gates per stage decreases and the pipeline becomes deeper, so that the portion of the clock cycle budgeted for clock uncertainty increases. In addition, production and distribution of the high-frequency clock to the increasing number of storage elements becomes progressively difficult due to various issues, such as load mismatch, power supply and substrate noise, and temperature variations. As a result, clock uncertainties occupy an increasing portion of the cycle time. The ability to reduce the impact of these uncertainties is one of the most important properties of the high-performance system.

The second important issue in high-performance digital systems is variation of the signal delays and the ability to absorb the delay of a signal that stretches beyond the time allotted to it by the pipeline stage. The ability of the pipeline to be flexible, thus allowing the extra delay to be absorbed by subsequent pipeline stages, without disrupting the correct operation is essential.


The clock uncertainties were of little consequence in the 1970s and 1980s, but in ...

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