Digital System Clocking: High-Performance and Low-Power Aspects

CHAPTER 7

SIMULATION TECHNIQUES

Results and conclusions about the performance of different CSEs depend significantly on the simulation setup and evaluation environment. CSE is just one of the elements in the pipeline, and has to be sized in such a way that the optimum performance for a given output load is achieved. The CSE output loads vary a lot across the processor core, depending on the level of parallelism in each unit and also on whether the CSE is on the critical path or not.

In modern data paths CSEs experience a heavy load due to the parallel execution units and increase in interconnect capacitance. It is the performance of these CSEs on the critical path that has the highest impact on the choice of processor cycle time. Hence, in high-speed designs, the design and evaluation of CSEs is focused on the elements on the critical path and often implicitly assumes such conditions during performance comparisons. On the other hand, there are a lot of CSEs that are placed on noncritical paths with relatively light loads. While these CSEs do not directly impact the performance of the processor, careful design of these elements can significantly reduce energy consumption and alleviate clock distribution problems.

The purpose of this chapter is to recommend simulation techniques that designers can use to evaluate the performance of CSEs, depending on the desired application. Most importantly, we try to build an understanding of the issues involved in creating a simulation environment ...