21
Debugging FPGA-based Video Systems
Chapter Outline
21.1.1 Check that the Design Meets Timing
21.1.2 Fix Your Design if it Does Not Meet Timing
21.2 The SystemConsole Debugger
21.3 Check That Clocks and Resets are Working
21.4 Clocked and Flow Controlled Video Streams
21.6 Converting from Clocked to Flow-controlled Video Streams
21.7 Converting from Flow-controlled to Clocked Video Streams
21.8 Free-running Streaming Video Interfaces
21.9 Insufficient Memory Bandwidth
In this chapter we will discuss some of the strategies you can use for debugging a video system built in an FPGA. The examples use Altera’s video debugging ...
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