Digital VLSI Design and Simulation with Verilog

Digital VLSI Design and Simulation with Verilog

by Suman Lata Tripathi, Sobhit Saxena, Sanjeet K. Sinha, Govind S. Patel
Released December 2021
Publisher(s): Wiley
ISBN: 9781119778042

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Book description

Master digital design with VLSI and Verilog using this up-to-date and comprehensive resource from leaders in the field

Digital VLSI Design Problems and Solution with Verilog delivers an expertly crafted treatment of the fundamental concepts of digital design and digital design verification with Verilog HDL. The book includes the foundational knowledge that is crucial for beginners to grasp, along with more advanced coverage suitable for research students working in the area of VLSI design. Including digital design information from the switch level to FPGA-based implementation using hardware description language (HDL), the distinguished authors have created a one-stop resource for anyone in the field of VLSI design.

Through eleven insightful chapters, you'll learn the concepts behind digital circuit design, including combinational and sequential circuit design fundamentals based on Boolean algebra. You'll also discover comprehensive treatments of topics like logic functionality of complex digital circuits with Verilog, using software simulators like ISim of Xilinx. The distinguished authors have included additional topics as well, like:

  • A discussion of programming techniques in Verilog, including gate level modeling, model instantiation, dataflow modeling, and behavioral modeling
  • A treatment of programmable and reconfigurable devices, including logic synthesis, introduction of PLDs, and the basics of FPGA architecture
  • An introduction to System Verilog, including its distinct features and a comparison of Verilog with System Verilog
  • A project based on Verilog HDLs, with real-time examples implemented using Verilog code on an FPGA board

    Perfect for undergraduate and graduate students in electronics engineering and computer science engineering, Digital VLSI Design Problems and Solution with Verilogalso has a place on the bookshelves of academic researchers and private industry professionals in these fields.

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    Table of contents

    1. Cover
    2. Title page
    3. Copyright
    4. Preface
    5. About the Authors
    6. 1 Combinational Circuit Design
      1. 1.1 Logic Gates
      2. 1.1.1 Universal Gate Operation
      3. 1.1.2 Combinational Logic Circuits
      4. 1.2 Combinational Logic Circuits Using MSI
      5. 1.2.1 Adders
      6. 1.2.2 Multiplexers
      7. 1.2.3 De-multiplexer
      8. 1.2.4 Decoders
      9. 1.2.5 Multiplier
      10. 1.2.6 Comparators
      11. 1.2.7 Code Converters
      12. 1.2.8 Decimal to BCD Encoder
      13. Review Questions
      14. Multiple Choice Questions
      15. Reference
    7. 2 Sequential Circuit Design
      1. 2.1 Flip-flops (F/F)
      2. 2.1.1 S-R F/F
      3. 2.1.2 D F/F
      4. 2.1.3 J-K F/F
      5. 2.1.4 T F/F
      6. 2.1.5 F/F Excitation Table
      7. 2.1.6 F/F Characteristic Table
      8. 2.2 Registers
      9. 2.2.1 Serial I/P and Serial O/P (SISO)
      10. 2.2.2 Serial Input and Parallel Output (SIPO)
      11. 2.2.3 Parallel Input and Parallel Output (PIPO)
      12. 2.2.4 Parallel Input and Serial Output (PISO)
      13. 2.3 Counters
      14. 2.3.1 Synchronous Counter
      15. 2.3.2 Asynchronous Counter
      16. 2.3.3 Design of a 3-Bit Synchronous Up-counter
      17. 2.3.4 Ring Counter
      18. 2.3.5 Johnson Counter
      19. 2.4 Finite State Machine (FSM)
      20. 2.4.1 Mealy and Moore Machine
      21. 2.4.2 Pattern or Sequence Detector
      22. Review Questions
      23. Multiple Choice Questions
      24. Reference
    8. 3 Introduction to Verilog HDL
      1. 3.1 Basics of Verilog HDL
      2. 3.1.1 Introduction to VLSI
      3. 3.1.2 Analog and Digital VLSI
      4. 3.1.3 Machine Language and HDLs
      5. 3.1.4 Design Methodologies
      6. 3.1.5 Design Flow
      7. 3.2 Level of Abstractions and Modeling Concepts
      8. 3.2.1 Gate Level
      9. 3.2.2 Dataflow Level
      10. 3.2.3 Behavioral Level
      11. 3.2.4 Switch Level
      12. 3.3 Basics (Lexical) Conventions
      13. 3.3.1 Comments
      14. 3.3.2 Whitespace
      15. 3.3.3 Identifiers
      16. 3.3.4 Escaped Identifiers
      17. 3.3.5 Keywords
      18. 3.3.6 Strings
      19. 3.3.7 Operators
      20. 3.3.8 Numbers
      21. 3.4 Data Types
      22. 3.4.1 Values
      23. 3.4.2 Nets
      24. 3.4.3 Registers
      25. 3.4.4 Vectors
      26. 3.4.5 Integer Data Type
      27. 3.4.6 Real Data Type
      28. 3.4.7 Time Data Type
      29. 3.4.8 Arrays
      30. 3.4.9 Memories
      31. 3.5 Testbench Concept
      32. Multiple Choice Questions
      33. References
    9. 4 Programming Techniques in Verilog I
      1. 4.1 Programming Techniques in Verilog I
      2. 4.2 Gate-Level Model of Circuits
      3. 4.3 Combinational Circuits
      4. 4.3.1 Adder and Subtractor
      5. 4.3.2 Multiplexer and De-multiplexer
      6. 4.3.3 Decoder and Encoder
      7. 4.3.4 Comparator
      8. Review Questions
      9. Multiple Choice Questions
      10. References
    10. 5 Programming Techniques in Verilog II
      1. 5.1 Programming Techniques in Verilog II
      2. 5.2 Dataflow Model of Circuits
      3. 5.3 Dataflow Model of Combinational Circuits
      4. 5.3.1 Adder and Subtractor
      5. 5.3.2 Multiplexer
      6. 5.3.3 Decoder
      7. 5.3.4 Comparator
      8. 5.4 Testbench
      9. 5.4.1 Dataflow Model of the Half Adder and Testbench
      10. 5.4.2 Dataflow Model of the Half Subtractor and Testbench
      11. 5.4.3 Dataflow Model of 2 × 1 Mux and Testbench
      12. 5.4.4 Dataflow Model of 4 × 1 Mux and Testbench
      13. 5.4.5 Dataflow Model of 2-to-4 Decoder and Testbench
      14. Review Questions
      15. Multiple Choice Questions
      16. References
    11. 6 Programming Techniques in Verilog II
      1. 6.1 Programming Techniques in Verilog II
      2. 6.2 Behavioral Model of Combinational Circuits
      3. 6.2.1 Behavioral Code of a Half Adder Using If-else
      4. 6.2.2 Behavioral Code of a Full Adder Using Half Adders
      5. 6.2.3 Behavioral Code of a 4-bit Full Adder (FA)
      6. 6.2.4 Behavioral Model of Multiplexer Circuits
      7. 6.2.5 Behavioral Model of a 2-to-4 Decoder
      8. 6.2.6 Behavioral Model of a 4-to-2 Encoder
      9. 6.3 Behavioral Model of Sequential Circuits
      10. 6.3.1 Behavioral Modeling of the D-Latch
      11. 6.3.2 Behavioral Modeling of the D-F/F
      12. 6.3.3 Behavioral Modeling of the J-K F/F
      13. 6.3.4 Behavioral Modeling of the D-F/F Using J-K F/F
      14. 6.3.5 Behavioral Modeling of the T-F/F Using J-K F/F
      15. 6.3.6 Behavior Modeling of an S-R F/F Using J-K F/F
      16. Review Questions
      17. Multiple Choice Questions
      18. References
    12. 7 Digital Design Using Switches
      1. 7.1 Switch-Level Model
      2. 7.2 Digital Design Using CMOS Technology
      3. 7.3 CMOS Inverter
      4. 7.4 Design and Implementation of the Combinational Circuit Using Switches
      5. 7.4.1 Types of Switches
      6. 7.4.2 CMOS Switches
      7. 7.4.3 Resistive Switches
      8. 7.4.4 Bidirectional Switches
      9. 7.4.5 Supply and Ground Requirements
      10. 7.5 Logic Implementation Using Switches
      11. 7.5.1 Digital Design with a Transmission Gate
      12. 7.6 Implementation with Bidirectional Switches
      13. 7.6.1 Multiplexer Using Switches
      14. 7.7 Verilog Switch-Level Description with Structural-Level Modeling
      15. 7.8 Delay Model with Switches
      16. Review Questions
      17. Multiple Choice Questions
      18. References
    13. 8 Advance Verilog Topics
      1. 8.1 Delay Modeling and Programming
      2. 8.1.1 Delay Modeling
      3. 8.1.2 Distributed-Delay Model
      4. 8.1.3 Lumped-Delay Model
      5. 8.1.4 Pin-to-Pin-Delay Model
      6. 8.2 User-Defined Primitive (UDP)
      7. 8.2.1 Combinational UDPs
      8. 8.2.2 Sequential UDPs
      9. 8.2.3 Shorthands in UDP
      10. 8.3 Task and Function
      11. 8.3.1 Difference between Task and Function
      12. 8.3.2 Syntax of Task and Function Declaration
      13. 8.3.3 Invoking Task and Function
      14. 8.3.4 Examples of Task Declaration and Invocation
      15. 8.3.5 Examples of Function Declaration and Invocation
      16. Review Questions
      17. Multiple Choice Questions
      18. References
    14. 9 Programmable and Reconfigurable Devices
      1. 9.1 Logic Synthesis
      2. 9.1.1 Technology Mapping
      3. 9.1.2 Technology Libraries
      4. 9.2 Introduction of a Programmable Logic Device
      5. 9.2.1 PROM, PAL and PLA
      6. 9.2.2 SPLD and CPLD
      7. 9.3 Field-Programmable Gate Array
      8. 9.3.1 FPGA Architecture
      9. 9.4 Shannon’s Expansion and Look-up Table
      10. 9.4.1 2-Input LUT
      11. 9.4.2 3-Input LUT
      12. 9.5 FPGA Families
      13. 9.6 Programming with FPGA
      14. 9.6.1 Introduction to Xilinx Vivado Design Suite for FPGA-Based Implementations
      15. 9.7 ASIC and Its Applications
      16. Review Questions
      17. Multiple Choice Questions
      18. References
    15. 10 Project Based on Verilog HDLs
      1. 10.1 Project Based on Combinational Circuit Design Using Verilog HDL
      2. 10.1.1 Full Adder Using Switches at Structural Level Model
      3. 10.1.2 Ripple-Carry Full Adder (RCFA)
      4. 10.1.3 4-bit Carry Look-ahead Adder (CLA)
      5. 10.1.4 Design of a 4-bit Carry Save Adder (CSA)
      6. 10.1.5 2-bit Array Multiplier
      7. 10.1.6 2 × 2 Bit Division Circuit Design
      8. 10.1.7 2-bit Comparator
      9. 10.1.8 16-bit Arithmetic Logic Unit
      10. 10.1.9 Design and Implementation of 4 × 16 Decoder Using 2 × Decoder
      11. 10.2 Project Based on Sequential Circuit Design Using Verilog HDL
      12. 10.2.1 Design of 4-bit Up/down Counter
      13. 10.2.2 LFSR Based 8-bit Test Pattern Generator
      14. 10.3 Counter Design
      15. 10.3.1 Random Counter that Counts Sequence like 2,4,6,8,2,8…and so On
      16. 10.3.2 Use of Task at the Behavioral-Level Model
      17. 10.3.3 Traffic Signal Light Controller
      18. 10.3.4 Hamming Code(h,k) Encoder/Decoder
      19. Review Questions
      20. Multiple Choice Questions
      21. References
    16. 11 SystemVerilog
      1. 11.1 Introduction
      2. 11.2 Distinct Features of SystemVerilog
      3. 11.2.1 Data Types
      4. 11.2.2 Arrays
      5. 11.2.3 Typedef
      6. 11.2.4 Enum
      7. 11.3 Always_type
      8. 11.4 $log2c() Function
      9. 11.5 System-Verilog as a Verification Language
      10. Review Questions
      11. Multiple Choice Questions
      12. Reference
    17. Index
    18. End User License Agreement

    Product information

    • Title: Digital VLSI Design and Simulation with Verilog
    • Author(s): Suman Lata Tripathi, Sobhit Saxena, Sanjeet K. Sinha, Govind S. Patel
    • Release date: December 2021
    • Publisher(s): Wiley
    • ISBN: 9781119778042