Digital VLSI Design and Simulation with Verilog

5 Programming Techniques in Verilog II

5.1 Programming Techniques in Verilog II

Verilog is a Hardware Description language (HDL) used to illustrate a digital system such as a microprocessor, flip-flops (F/Fs), network switch, memory, etc. The Verilog language can be used to describe any digital hardware at any level. The circuit designs developed using HDL are not dependent on technology, are more helpful than schematics and are very simple for debugging and designing, especially for huge circuits. In this chapter, the dataflow model of the circuit is described with the help of different types of circuits.

5.2 Dataflow Model of Circuits

Dataflow modeling does not explain the combinational circuits logic gate. It describes the Boolean funtion of output variable in terms of input variables using operators available in the Verilog library. Here, the data flows from register to register. It requires lesser design steps in comparison to the gate-level model. A number of operators are used by dataflow modeling for the operator to produce the desired results. The model makes use of continuous assignments with the keyword “assign.”

HDL Operators for the dataflow model include:

• + Binary addition
• − Binary subtraction
• & Bit – wise AND
• | Bit – wise OR
• ^ Bit – wise XOR
• ~ Bit – wise NOT
• ?: Conditional

5.3 Dataflow Model of Combinational Circuits

Adder and Subtractor

Multiplexer

Decoder

Comparator

5.3.1 Adder and Subtractor

5.3.1.1 Half Adder

In a half-adder circuit, X and Y are the ...