Digital VLSI Design and Simulation with Verilog

6 Programming Techniques in Verilog II

6.1 Programming Techniques in Verilog II

The behavioral model of a circuit is a representation of all blocks in the algorithmic level. In the behavioral model, the keyword is always used with different procedural assignments. In this model, the output of the circuit is defined as reg. Verilog HDL mainly has four design levels with the behavioral model as the highest level of abstraction. The behavioral model uses algorithm or truth tables for the implementation of digital circuit design. It does not need information about logic block representation [1]. Both combination and sequential circuit designs can be done at the behavioral level. The programming concept in the behavioral model is almost similar to C language.

In the highest level of the behavioral model, each statement execution is performed through a triggering signal. The statement execution is initiated through the keywords always or initial, called procedural statements. These procedural statements are used to define the activity flow of the particular logic block. The nesting of always and initial blocks are not allowed in Verilog HDL. The initial blocks are mainly used to assign values to input and output variables.

Properties of behavioral statements are:

• Each initial block executes only once during the simulation and statements start executions at a zero instant of time.
• For multiple initial blocks, the execution starts at zero instant.
• The always block also starts at execution ...