Digital VLSI Design and Simulation with Verilog

8 Advance Verilog Topics

8.1 Delay Modeling and Programming

In actual hardware, different delays exist and broadly, delays can be divided into two types i.e., gate delays and wire or interconnection delays. During the design of any circuit, delays must be considered in the programming to match with actual hardware timings. With advancement of technology, timing constraints become crucial and hence need to be taken care of while programming. Verilog also has the facility to introduce delay while designing the circuits [1–2].

8.1.1 Delay Modeling

Three different types of delay modeling are available in Verilog:

1. Distributed-delay modeling
2. Lumped-delay modeling
3. Pin-to-Pin-delay modeling or Path-delay modeling.

8.1.2 Distributed-Delay Model

This type of delay is specified with each element of the circuit. In the case of combinational circuits, each gate has its propagation delay and is specified within the statement of all gates used in the gate-level modeling style of Verilog.

As an example in the following circuit diagram shown in Figure 8.1, the distributed delay is indicated inside the image of all the gates. The Verilog code for the same is shown in Program P8.1.

Figure 8.1 A simple combinational circuit indicating distributed delay.

//Program P8.1
module distributed_delay (F,A,B,C,D);
output F;
input A,B,C,D;
wire w1,w2;
or #3 x1(w1,A,B);
or #3 x2(w2,C,D);
and #2 x3(F,w1,w2); ...