Digital VLSI Design and Simulation with Verilog

11 SystemVerilog

11.1 Introduction

After studying Verilog in detail, let’s go one step further and learn about SystemVerilog. Due to some additional features compared to Verilog, this becomes attractive for fast-evolving technologies and industries are now more interested. SystemVerilog obtained standardization by the IEEE 1800 in 2018 as a hardware description and hardware verification language [1] which is an extension of Verilog used to model, design, simulate, test, and implement electronic systems. For better understanding, the features of SystemVerilog are discussed in comparison with Verilog.

11.2 Distinct Features of SystemVerilog

There are many extended features that make the SystemVerilog a better hardware designing and verification language than Verilog. A few of these are:

1. Non-blocking and blocking operators (≤ and = respectively) can be used for arrays.
2. Input, output, and inout ports support more formats of data types such as real, struct, and enum. Multi-dimensionality is also supported.
3. Equipped with the automatic declaration of variable inside the loop statement. Addition of do/while loop in the while-loop construct.
4. Many new operators similar to C-language are supported in SystemVerilog. A few of these are:
   1. Increment/decrement operators viz. i++, ++i, i–, –i
   2. Compound-assignment operators viz. i + = x, i- = x, i* = x, i/ = x, i% = x, i≪ = x, i≫ = x, i& = x, i^ = x, i| = x.
5. New features in the fork-join block have been added viz. join_none & join_any.
6. It is ...