Dynamic RAM

4

Advanced DRAM Cell Transistors

4.1    Introduction

As DRAM technology crosses the sub-100 nm node, planar transistors are not able to maintain level of on-current. Also, transistors do not satisfy the overall leakage current limit, mainly due to high electric field on account of shrinking of channel length, while array voltage was not changing with every lithographic generation. A common remedy used in transistors was to design with increased channel doping concentration to increase threshold voltage, so as to reduce sub-threshold current—a substantial component of the leakage current. However, increased doping level causes high junction leakage current at the storage node and also reduces the current drive capability of the transistor. ...