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Efficient C++ Performance Programming Techniques by David Mayhew, Dov Bulka

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Memory Hierarchies

Any discussion of performance must, in the end, center on memory usage and memory usage patterns. Frequently the most significant aspects of algorithmic complexity are centered on the number and type of memory accesses an algorithm requires. It has never been more true than it is now that calculation is fast and access is slow.

There are now typically at least five levels in the memory hierarchy of the average computer. Some of the main levels of the memory hierarchy sometimes contain sublevels. The memory hierarchy, from its fastest (lowest access time) to its slowest (highest access time) consists of registers, L1 (level one) on-chip cache, L2 (level two) off-chip cache, main memory (semiconductor dynamic random access memory ...

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