Efficient C++ Performance Programming Techniques

Registers: Kings of Memory

Registers are the lowest latency, highest bandwidth, lowest specification overhead entities in the memory hierarchy. As already indicated, they are effectively at least twice as fast as an L1 cache. Typically, register sets are at least triple ported; that is, a register set typically can read two operands and write one operand every clock cycle. This means that a simple 600MHz, 64-bit RISC architecture would have a maximum register bandwidth of approximately 14.4 gigabytes per second. This is three to six times greater than a respectable L1 cache's bandwidth and more than 30 times the effective bandwidth of a 64-bit wide, 100MHz external DRAM interface.

Registers are directly addressed within machine code statements. ...