Chapter 3. Design for testability
About This Chapter
Design for testability (DFT) has become an essential part for designing very-large-scale integration (VLSI) circuits. The most popular DFT techniques in use today for testing the digital portion of the VLSI circuits include scan and scan-based logic built-in self-test (BIST). Both techniques have proved to be quite effective in producing testable VLSI designs. In addition, test compression, a supplemental DFT technique for scan, is growing in importance for further reduction in test data volume and test application time during manufacturing test.
To provide readers with an in-depth understanding of the most recent DFT advances in scan, logic BIST, and test compression, this chapter covers ...