Electronic Design Automation

5.2. Fundamentals of High-Level Synthesis

In a nutshell, high-level synthesis (HLS) takes as input an algorithmic description (e.g., in C/C++) and generates as output a hardware implementation of a microarchitecture (e.g., in VHDL/Verilog). Algorithmic languages such as C/C++ capture what we refer to as the behavioral-level (or high-level) description of the design; whereas hardware description languages such as VHDL/Verilog capture the register-transfer level (RTL) description of the design.

Figure 5.4a shows a typical example of an input behavioral level description. Here a design is described as a sequence of statements and expressions operating on program variables. Such description captures the function of the design without any hardware ...