Electronic Design Automation

8.2.2. Timing models

Delay is a fact of life for all electrical components, including logic gates and interconnection wires. In this section, we discuss the commonly used gate and wire delay models.

8.2.2.1. Transport delay

The transport delay refers to the time duration it takes for the effect of gate input changes to appear at gate outputs. Several transport delay models characterize this phenomenon from different aspects.

The nominal delay model specifies the same delay value for the output rising and falling transitions. Consider the AND gate G in Figure 8.4 as an example. Here B is fixed at 1; thus, the output of G is only affected by A. Assuming that G has a nominal delay of d^N = 2 ns and A is pulsed to 1 for 1 ns, the corresponding ...