Electronic Design Automation

8.4. Hard Ware-Accelerated Logic Simulation

As the IC density and complexity continue growing, verifying the correctness of a new design before its first silicon has become the key to success. Although versatile and accurate, logic simulation is too slow for large designs, not to mention SOC designs that necessitate hardware/software (HW/SW) co-simulation.

Various hardware-acceleration techniques have been developed to bridge the gap between the IC complexity and logic simulation efficiency. A simplified block diagram of an FPGA-based hardware emulator is illustrated in Figure 8.15. (In some hardware emulators, programmable application-specific integrated circuits [ASICs] are used instead of FPGAs.) The hardware emulator (called emulator hereafter) ...