9.2. Verification Hierarchy
Modern IC designs typically follow a top-down implementation flow in which a system is hierarchically partitioned into components. Each partitioning boundary defines the level of the design components. Within the hierarchy, verification tasks need to be performed before individual components are assembled. The V diagram in Figure 9.2 illustrates the design, verification, and integration flow starting from the system/board level, through the chip and core/unit levels, to the designer level.
FIGURE 9.2. V diagram of design, verification, and integration.
A generic verification flow [Palnitkar 2003a] for each level ...
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