13.3.3. Clock tree synthesis
Two problems relate to the synthesis of a clock net: (1) the determination of a feasible clock schedule that defines the arrival times of the clock signals at the clock pins, and (2) the physical layout of the clock network that realizes the clock schedule. In the context of clock synthesis, a clock schedule is feasible if it meets the performance requirement without causing race hazards in the system operation. A physical clock network realizes the clock schedule if the clock signal arrives at the registers at the respective arrival times specified by the clock schedule. We refer to the first problem as that of clock skew scheduling and the second as that of clock routing.
13.3.3.1. Clock skew scheduling
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