R13.3 Clock Network Design
[Anderson 2001] C.J. Anderson, J. Petrovick, J.M. Keaty, J. Warnock, G. Nussbaum, J.M. Tendier, C. Carter, S. Chu, J. Clabes, J. DiLullo, P. Dudley, P. Harvey, B. Krauter, J. LeBlanc, P.-F. Lu, B. McCredie, G. Plum, P.J. Restle, S. Runyon, M. Scheuermann, S. Schmidt, J. Wagoner, R. Weiss, S. Weitzel, B. Zoric, Physical design of a fourth-generation POWER GHz microprocessor Proc. IEEE Int. Solid-State Circuits Conf. February 2001, 232-233
[Bailey 1998] D. Bailey, B. Benschneider, Clocking design and analysis for a 600-MHz Alpha microprocessor IEEE J. on Solid-State Circuits 33 11 November 1998, 1627-1633
[Boese 1992] K.D. Boese, A.B. Kahng, Zero-skew clock routing trees with minimum wire-length ...
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