December 2021
Intermediate to advanced
336 pages
9h 20m
English
Content preview from Electronic Packaging Science and Technology
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82.5D/3D System‐in‐Packaging Integration
8.1 Introduction
On the brief history of computing hardware, it has moved from vacuum tubes to discrete devices, then to integrated circuits (ICs). The chips are getting larger and larger, following the Moore’s Law, so the chip capacity and performance increases; they are driven by the demands of applications. In the near future, these application demands are driving the advance to vertical stacking in chips and memories. We have mentioned the vertical trending in Section 6.6 for modern chips and packages: 3D IC packaging, 3D IC integration, and 3D silicon integration. With the practical 3D solutions consideration in modern technology, we shall focus on the category of 3D IC integration in this chapter.
Unlike 3D Si integration, 3D IC integration stacks up chips in the vertical direction with through silicon vias (TSVs), thin chips/interposers, and micro‐bumps to achieve high performance, low power, wide bandwidth, small form factor, and hopefully low cost [1]. Among 3D IC integration solutions, the so‐called 2.5D IC utilizes a piece of dummy silicon (or glass), people call it interposer, with TSVs/TGVs for the communication of signals and power delivery. Such designs have become the savior in high‐performance computing devices due to its lower cost compared to genuine 3D manufacturing chips. We shall discuss the concept and format of 2.5D IC designs through Sections 8.2–8.4.
On the other hand, the genuine 3D IC integration lies in real ...
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