Embedded SoPC Design with Nios II Processor and Verilog Examples

CHAPTER 11

PREDESIGNED NIOS II I/O PERIPHERALS

The I/O peripherals of Nios II are soft cores and can be incorporated into a Nios II system and eventually synthesized into the same FPGA chip. Altera provides a set of commonly used I/O peripherals that can be easily configured and integrated in SOPC Builder. In this chapter, we examine the structure and use of three peripherals for general input and output interface, serial communication, and timing, and use them to construct a more sophisticated Nios II system.

Software complexity grows as I/O devices become more involved. A common approach to alleviate the problem is to confine the low-level I/O transactions in a collection of routines, sometimes know as device drivers, and shield the details from application programs. In this chapter, we use an enhanced fashing-LED system to demonstrate the use of new I/O cores and the development of ad hoc drivers. We intentionally avoid Altera's predesigned HAL-compliant drivers and postpone the coverage to Chapter 12.

11.1 OVERVIEWS

Like the Nios II processor, its I/O peripherals are usually described by HDL codes and implemented as soft cores. For a commonly used I/O function, a predesigned core is usually available and we just need to instantiate it when a Nios II system is constructed. For a specialized I/O peripheral, we may need to design it from scratch and then integrate the circuit with the processor. Altera provides a set of I/O cores for commonly used I/O functionalities.

When we ...