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Embedded Systems Architecture by Daniele Lacamera

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Deep-sleep configuration

To select between stop and standby mode, and to set up a number of parameters related to the deep-sleep modes, our reference platform provides a power controller, mapped in the internal peripherals region, at address 0x40007000. The controller consists of two registers:

  • PWR_CR (control register) at offset 0
  • PWR_SCR (status and control register) at offset 4

The relevant parameters that can be configured in these two registers are the following:

  • Regulator Voltage-scaling Output Selection (VOS), set through PWR_CR bit 14. When active, saves extra power in normal running mode, by configuring the internal regulator to produce a slightly lower voltage for the CPU core logic. This feature is only available if the target ...

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