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Embedded Systems Architecture by Daniele Lacamera

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Peripherals interrupt configuration

Each interrupt line can be enabled and disabled through the NVIC Interrupt Set/Clear Enable registers, NVIC_ISER, NVIC_ICER, located at address 0xE000E100 and 0xE000E180, respectively. If the target supports more than 32 external interrupts, arrays of 32-bit registers are mapped at the same locations. Each bit in the registers is used to activate a predefined interrupt line, associated to the bit position in that specific register. For example, on an STM32F4 microcontroller, in order to activate the interrupt line for the SPI controller SPI1, which is associated with number 35, the fourth bit should be set on the second register in the NVIC_ISER area.

The generic NVIC function, to enable the interrupt, ...

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