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Embedded Systems Architecture by Daniele Lacamera

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Clock stretching

We have observed that the master is the only one driving the SCL signal during I2C transactions. This is always true, except when the slave is not yet ready to transmit the requested data from the master. In this particular case, the slave may decide to delay the transaction by keeping the clock line pulled low, which results in the transaction being put on hold. The master recognizes its inability to oscillate the clock, as releasing the SCL to a floating state does not result in a change to a high logic level on the bus. The master will keep trying to release SCL to its natural high position until the requested data is finally available on the slave, which eventually releases the hold on the line.

The transmission can now ...

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